1. Field of the Invention
The present invention relates to a structure of a power MOSFET semiconductor device high in breakdown voltage and low in resistance and to a method of manufacturing the device.
2. Description of Related Art
FIG. 6 is a sectional view of a conventional power MOSFET. In order to attain high breakdown voltage and low on-resistance, so-called body diffusion is partially incorporated into a drift region of a drain in a structure. During the time the MOSFET is off, depletion layers extend from both sides of the deep body diffusion to contact each other in the middle. Specifically, in this case the drift region under a gate electrode 108 completely constitutes the depletion layer to a depth substantially equal to that of the deep body diffusion. Since a depletion layer width is very large, electric field relaxing action is large, and breakdown voltage can be enhanced without decreasing an impurity density of the drift region. On the other hand, since the density of the drift region does not need to be lowered, it is unnecessary to lower a drift parasitic resistance during an on state, and it is also possible to keep MOSFET on-resistance low.
To achieve a conventional structure, however, epitaxial growth and selective formation of a deep body region have to be performed a plurality of times, and with an increase in the number of manufacture steps, increase in manufacture cost and lengthening of manufacture period result.
For example, when a drain breakdown voltage of several hundreds of volts or more is realized, the deep body region needs a depth of five to a dozen micrometers, but in this case the epitaxial growth and selective formation of the deep body region need to be repeated around six times.
In order to solve the aforementioned problems, the present invention uses the following means.
(1) There is provided a semiconductor device comprising a high impurity concentration first conductivity type semiconductor substrate, a low impurity concentration first conductivity type semiconductor layer formed on a surface of the semiconductor substrate, a trench selectively formed in a surface of the low impurity concentration semiconductor layer, a low impurity concentration second conductivity type semiconductor diffusion layer formed on a side wall and a bottom wall of the trench, a relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer partially overlapped with the second conductivity type semiconductor diffusion layer and selectively formed on the surface of the low impurity concentration first conductivity type semiconductor, a high impurity concentration first conductivity type semiconductor diffusion layer selectively formed in the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer, a gate insulation film formed on the low impurity concentration first conductivity type semiconductor layer and the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer, and a gate electrode selectively formed on the gate insulation film.
(2) The inside of the trench formed in the low impurity concentration first conductivity type semiconductor layer is filled with an insulation film in the semiconductor device.
(3) The inside of the trench formed in the low impurity concentration first conductivity type semiconductor layer is filled with first conductivity type polycrystalline silicon in the semiconductor device.
(4) A manufacture method of a semiconductor device, comprising steps of: forming a low impurity concentration first conductivity type semiconductor layer on a high impurity concentration first conductivity type semiconductor substrate by epitaxial growth, selectively forming a trench in a surface of the low impurity concentration semiconductor layer, forming a low impurity concentration second conductivity type semiconductor diffusion layer on a side wall and a bottom wall of the trench, partially overlapping a relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer with the second conductivity type semiconductor diffusion layer disposed on the side wall and the bottom wall of the trench and selectively forming the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer in the low impurity concentration first conductivity type semiconductor layer, selectively forming a high impurity concentration first conductivity type semiconductor diffusion layer in the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer, forming a gate insulation film on the low impurity concentration first conductivity type semiconductor layer and the relatively shallow low impurity concentration second conductivity type semiconductor diffusion layer, and selectively forming a gate electrode on the gate insulation film.
(5) The manufacture method of the semiconductor device further comprises a step of filling the inside of the trench formed in the low impurity concentration first conductivity type semiconductor layer with an insulation film.
(6) The manufacture method of the semiconductor device further comprises a step of filling the inside of the trench formed in the low impurity concentration first conductivity type semiconductor layer with polycrystalline silicon.
(7) The step of forming the low impurity concentration second conductivity type semiconductor diffusion layer on the side wall and the bottom wall of the trench comprises solid phase diffusion from an oxide film including an impurity in the manufacture method of the semiconductor device.
(8) The step of forming the low impurity concentration second conductivity type semiconductor diffusion layer on the side wall and the bottom wall of the trench comprises solid phase diffusion from polycrystalline silicon including an impurity in the manufacture method of the semiconductor device.
(9) The step of forming the low impurity concentration second conductivity type semiconductor diffusion layer on the side wall and the bottom wall of the trench comprises a molecular layer doping process in the manufacture method of the semiconductor device.